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TECHNICAL DATA SL74LVU04 Hex Inverter The 74LVU04 is a low-voltage, Si-gate CMOS device and is pin compatible with the 74HCU04. The 74LVU04 is a general purpose hex inverter. Each of the six inverters is a single stage with unbuffered outputs. * * * * Wide Operating Voltage: 1.0/5.5 V Optimized for Low Voltage applications: 1.0/3.6 V Accepts TTL input levels between VCC =2.7 V and VCC =3.6 V Low Input Current 14 1 14 1 N SUFFIX PLASTIC D SUFFIX SOIC ORDERING INFORMATION SL74LVU04N Plastic SL74LVU04D SOIC SL74LVU04 Chip TA = -40 / 125 C for all packages LOGIC DIAGRAM PIN ASSIGNMENT FUNCTION TABLE Input A L H PIN 14 =VCC PIN 7 = GND Output Y H L SLS System Logic Semiconductor 1 SL74LVU04 MAXIMUM RATINGS * Symbol VCC IIK * 1 2 Parameter DC supply voltage (Referenced to GND) DC input diode current DC output diode current DC output source or sink current -bus driver outputs DC VCC current for types with - bus driver outputs DC GND current for types with - bus driver outputs Power dissipation per package, plastic DIP+ SOIC package+ Storage temperature Lead temperature, 1.5 mm from Case for 10 seconds (Plastic DIP ), 0.3 mm (SOIC Package) Value -0.5 / +7.0 20 50 25 50 50 750 500 -65 / +150 260 Unit V mA mA mA mA mA mW C C IOK * IO * ICC IGND PD 3 Tstg TL * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 12 mW/C from 70 to 125C SOIC Package: : - 8 mW/C from 70 to 125C * 1: VI < -0.5V or VI > VCC+0.5V * 2: Vo < -0.5V or Vo > VCC+0.5V * 3: -0.5V < Vo < VCC+0.5V RECOMMENDED OPERATING CONDITIONS Symbol VCC VIN, VOUT TA tr, t f Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage, Output Voltage (Referenced to GND) Operating Temperature, All Package Types Input Rise and Fall Time 1.0 VVCC <2.0 V 2.0 VVCC <2.7 V 2.7 VVCC <3.6 V 3.6 VVCC 5.5 V Min 1.0 0 -40 0 0 0 0 Max 5.5 VCC +125 500 200 100 50 Unit V V C ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND(VIN or VOUT)VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. SLS System Logic Semiconductor 2 SL74LVU04 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Test Conditions VCC, V 1.2 2.0 2.7 3.0 3.6 4.5 5.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 VI = VIH or VIL I0=-100 iA 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 1.2 2.0 2.7 3.0 3.6 4.5 5.5 3.0 4.5 5.5 min 1.0 1.6 2.4 2.4 2.4 3.6 4.4 1.05 1.85 2.55 2.85 3.45 4.35 5.35 2.48 3.70 0.2 0.4 0.5 0.5 0.5 0.9 1.1 0.15 0.15 0.15 0.15 0.15 0.15 0.15 0.33 0.40 -0.1 Guaranteed Limit 25C max -40C / 85C min 1.0 1.6 2.4 2.4 2.4 3.6 4.4 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.40 3.60 0.2 0.4 0.5 0.5 0.5 0.9 1.1 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.40 0.55 -1.0 max -40C / 125C min 1.0 1.6 2.4 2.4 2.4 3.6 4.4 1.0 1.8 2.5 2.8 3.4 4.3 5.3 2.20 3.50 0.2 0.4 0.5 0.5 0.5 0.9 1.1 0.2 0.2 0.2 0.2 0.2 0.2 0.2 0.50 0.65 -1.0 iA V max V Unit Symbol Parameter VIH High-Level Input Voltage VIL Low -Level Input Voltage V VOH High-Level Output Voltage V VI = VIH or VIL I0=-6.0 mA VI = VIH or VIL I0=-12 mA VOL Low-Level Output Voltage VI = VIH or VIL I0=100 iA VI = VIH or VIL I0=6.0 mA VI = VIH or VIL I0=12 mA IIL Low-Level Input Leakage Current VI=0 V DC ELECTRICAL CHARACTERISTICS (continuation) Symbol Parameter Test Conditions VCC, 25C Guaranteed Limit -40C / 85C -40C / 125C Unit SLS System Logic Semiconductor 3 SL74LVU04 V IIH High-Level Input Leakage Current Quiescent Supply Current (per Package) Additional Quiescent Supply Current on input VI= VNN 5.5 min - max 0.1 min - max 1.0 min - max 1.0 ICC VI=0 A or VNN IO = 0 iA VI = VNN - 0.6V 5.5 - 4.0 - 20 - 40 iA ICC1 2.7 3.6 - 0.2 0.2 - 0.5 0.5 - - 0.85 0.85 mA AC ELECTRICAL CHARACTERISTICS (CL=50 pF, t LH =t HL = 2.5 ns, RL=1 kU) Test Conditions VI=0 V or V1 tLH = tHL =2.5 ns N L = 50 pF RL = 1 kU VCC V 1.2 2.0 2.7 3.0 4.5 Min Guaranteed Limit 25C max 70 22 16 13 11 -40C / 85C min max 80 26 19 15 13 -40C / 125C min max 100 31 23 18 16 ns Unit Symbol Parameter tPHL (t PLH) Propagation Delay, Input A to Output Y (Figure 1 ) CI CPD Input Capacitance 5.5 - 7.0 - - - - pF pF Power Dissipation Capacitance (Per Inverter) O A=25N, VI=0V or VCC 36 Used to determine the no-load dynamic power consumption: PD = CPDVCC2fI+ (CLVCC2fo), fI - input frequency, fo - output frequency (MHz) (CLVCC2fo) - sum of the outputs SLS System Logic Semiconductor 4 SL74LVU04 tH L tL H 0.9 VX 0.1 0.9 VX 0.1 V1 Input A tP HL GND tP LH VOH Output Y VX=0.5 VCC VY VY VOL Figure 1. Switching Waveforms VC C VI PULSE GENERATOR DEVICE UNDER TEST VO Termination resistance RT - should be equal to ZOUT of pulse generators CL RL RT Figure 2. Test circuit SLS System Logic Semiconductor 5 SL74LVU04 CHIP PAD DIAGRAM SL74LVU04 1.33 0.03 13 12 11 10 09 1.42 0.03 14 08 07 01 02 03 04 05 06 Chip marking IN74LVU04 (x=0.130; y=0.130) Pad size 0.108 x 0.108 mm (Pad size is given as per metallization layer) Thickness of chip 0.46 0,02 mm PAD LOCATION Pad No 01 02 03 04 05 06 07 08 09 10 11 12 13 14 Symbol A1 Y1 A2 Y2 A3 Y3 GND Y4 A4 Y5 A5 Y6 A6 VCC X 0.130 0.130 0.381 0.616 0.881 1.116 1.115 1.115 1.115 0.804 0.569 0.378 0.143 0.130 Y 0.463 0.230 0.126 0.126 0.126 0.126 0.631 0.846 1.181 1.194 1.194 1.194 1.194 0.813 SLS System Logic Semiconductor 6 |
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